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integrated silicon solution, inc. www.issi.com 1 rev.? 00e 09/08/2010 copyright ? 2010 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the lat- est version of this device specifcation before relying on any published information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason- ably be expected to cause failure of the life support system or to signifcantly affect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances is43dr32800a, is43/46dr32801a preliminary ? information september?2010 8mx32 ? ?? ? ??? 256mb?ddr2?dram features ? v dd = 1.8v 0.1v, v ddq = 1.8v 0.1v ? jedec standard 1.8v i/o (sstl_18-compatible) ? double data rate interface: two data transfers per clock cycle ? differential data strobe (dqs, dqs) ? 4-bit prefetch architecture ? on chip dll to align dq and dqs transitions with ck ? 4 internal banks for concurrent operation ? programmable cas latency (cl) 3, 4, 5, and 6 supported ? posted cas and programmable additive latency (al) 0, 1, 2, 3, 4, and 5 supported ? write latency = read latency - 1 tck ? programmable burst lengths: 4 or 8 ? adjustable data-output drive strength, full and reduced strength options ? on-die termination (odt) options ? ? ? confguration: 8m x 32 (is43dr32800a standard page - 4k refresh) 8m x 32 (is43/46dr32801a reduced page - 8k refresh) ? package: x32: 126 wbga ? timing C cycle time 3.0ns @cl=5, ddr2-667d 3.75ns @cl=4, ddr2-533c 5.0ns @cl=3, ddr2-400b ? temperature range: commercial (0c tc 85c; 0c t a 70c) industrial (C40c tc 95c; C40c t a 85c) automotive, a1 (C40c tc 95c; C40c t a 85c) automotive, a2 (C40c tc 105c; C40c t a 105c) tc = case temp, t a = ambient temp description issi's 256mb ddr2 sdram uses a double-data-rate architecture to achieve high-speed operation. the double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the i/o balls. the 256mb ddr2 sdram is provided in a wide bus x32 format, designed to offer a smaller footprint and support compact designs. parameter 8m x 32 8m x 32 standard page size option reduced page size option confguration 2m x 32 x 4 banks 2m x 32 x 4 banks refresh count 4k/64ms 8k/64ms row addressing a0-a11 a0-a12 column addressing a0-a8 a0-a7 bank addressing ba0, ba1 ba0, ba1 precharge addressing a10/ap a10/ap address? table speed?grade -37c -5b trcd 15 15 trp 15 15 trc 60 55 tras 45 40 tck @cl=3 5 5 tck @cl=4 3.75 5 tck @cl=5 3.75 5 tck @cl=6 3.75 5 key? timing? parameters
2 integrated silicon solution, inc. www.issi.com rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a general?description read and write accesses to the ddr2 sdram are burst oriented; accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0-ba1 select the bank; a0-a11/a12 select the row and a0-a7/a8 select the column). the address bits registered coincident with the read or write command are used to select the starting column location for the burst access and to determine if the auto precharge command is to be issued. prior to normal operation, the ddr2 sdram must be initialized. the following sections provide detailed information covering device initialization, register defnition, command descriptions and device operation. functional?block?d iagram column decoder column decoder i/o gate & mask logic memory cell array bank 0 sense amp mode registers row address latch burst counter multiplexer refresh controller self refresh controller refresh counter bank control logic row decoder column decoder memory cell array bank 0 row address buffer input data buffer output data buffer dm0 C dm3 a0 C an, ba0 C ba1 dq0 C dq31 row decoder column address buffer column address latch sense amp column decoder dll data strobe generator odt circuit dqs0 C dqs3, command decoder & clock generator ck ck cke odt cs ras cas we dqs0 C dqs3 notes: 1.) an: n = no. of address pins C 1
integrated silicon solution, inc. www.issi.com 3 rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a symbol? type ? function? ck, ck input clock: ck and ck are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck. output (read) data is referenced to the crossings of ck and ck (both directions of crossing). cke input clock enable: cke high activates, and cke low deactivates, internal clock signals and device input buffers and output drivers. taking cke low provides precharge power-down and self refresh operation (all banks idle), or active power-down (row active in any bank). cke is synchronous for power down entry and exit, and for self refresh entry. cke is asynchronous for self refresh exit. after vref has become stable during the power on and initialization sequence, it must be maintained for proper operation of the cke receiver. for proper self-refresh entry and exit, vref must be maintained to this input. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck, odt and cke are disabled during power-down. input buffers, excluding cke, are disabled during self refresh. cs input chip select: all commands are masked when cs is registered high. cs provides for external rank selection on systems with multiple ranks. cs is considered part of the command code. odt input on die termination: odt (registered high) enables termination resistance internal to the ddr2 sdram. when enabled, odt is applied to each dq, dqs, dqs, dqm signals. the odt pin will be ignored if the emr(1) is programmed to disable odt. ras, cas, we input command inputs: ras, cas and we (along with cs) defne the command being entered. (dm0-dm3) input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. the function of dm is enabled by emrs command to emr(1). ba0 - ba1 input bank address inputs: ba0 - ba1 defne to which bank an active, read, write or precharge command is being applied. bank address also determines if the mode register or one of the extended mode registers is to be accessed during a mrs or emrs command cycle. a0 - a12 input address inputs: provide the row address for active commands and the column address and auto precharge bit for read/write commands to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba0 - ba1. the address inputs also provide the op-code during mrs or emrs commands. standard page option only: a12 is not used for addressing, but is necessary as an input for the setting of the mode register (mrs) and extended mode registers (emr). if not implemented for mrs/emr, a12 can be left connected to vss. it must not be left foating. pin?description?table
4 integrated silicon solution, inc. www.issi.com rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a symbol? type ? function? dq0-31 input/ output data input/output: bi-directional data bus. dqs, (dqs) (dqs 0-3, dqs 0-3) input/ output data strobe: output with read data, input with write data. edge-aligned with read data, centered in write data. the data strobes dqs(n) may be used in single ended mode or paired with optional complementary signals dqs(n) to provide differential pair signaling to the system during both reads and writes. a control bit at emr(1)[a10] enables or disables all complementary data strobe signals. dqs0 corresponds to the data on dq0-dq7 dqs1 corresponds to the data on dq8-dq15 dqs2 corresponds to the data on dq16-dq23 dqs3 corresponds to the data on dq24-dq31 nc no connect: no internal electrical connection is present. vddq supply dq power supply: 1.8 v +/- 0.1 v vssq supply dq ground vddl supply dll power supply: 1.8 v +/- 0.1 v vssdl supply dll ground vdd supply power supply: 1.8 v +/- 0.1 v vss supply ground vref supply reference voltage
integrated silicon solution, inc. www.issi.com 5 rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a pin? configuration? 126-ball bga for x32 (top view) (11mm x 14mm body, 0.8mm ball pitch) package code: b 1 2 3 4 5 6 7 8 9 10 11 12 a b c d e f g h j k l m n p r s dq0 vddq dq3 vddq dq5 vddq ras cs a10 a9 vddq dq21 vddq dq19 vddq dq16 vdd dq1 vssq dq4 vssq dq7 we cas a3 dq23 vssq dq20 vssq dq17 vdd vssq dq2 vssq dqs0 vssq dm0 cke vdd a1 a5 dm2 vssq dqs2 vssq dq18 vssq vs s vddq dqs0 vddq dq6 vs s odt vddl a7 a12 vs s dq22 vddq dqs2 vddq vs s vs s vddq dqs1 vddq dq14 vdd vref vssdl a2 nc vdd dq30 vddq dqs3 vddq vs s vssq dq10 vssq dqs1 vssq dm1 nc vs s a0 a11 dm3 vssq dqs3 vssq dq26 vssq dq8 vddq dq11 vddq dq13 vddq ba 0 ba1 a6 a8 vddq dq29 vddq dq27 vddq dq24 vdd dq9 vssq dq12 vssq dq15 ck ck a4 dq31 vssq dq28 vssq dq25 vdd not populated pin?name function pin?name function a0 to a12 address inputs odt odt control ba0, ba1 bank select vdd supply voltage for internal circuit dq0 to dq31 data input/output vss ground for internal circuit dqs0 to dqs3 differential data strobe vddq supply voltage for dq circuit /dqs0 to /dqs3 /cs chip select vssq ground for dq circuit /ras, /cas, /we command input vref input reference voltage cke clock enable vddl supply voltage for dll circuit ck, /ck differential clock input vssdl ground for dll circuit dm0 to dm3 write data mask nc no connection
6 integrated silicon solution, inc. www.issi.com rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a electrical?specifications absolute? maximum?dc?ratings symbol? parameter ? rating? units? notes v dd voltage on vdd pin relative to vss - 1.0 v ~ 2.3 v v 1,3 v ddq voltage on vddq pin relative to vss - 0.5 v ~ 2.3 v v 1,3 v ddl voltage on vddl pin relative to vss - 0.5 v ~ 2.3 v v 1,3 v in , v out voltage on any pin relative to vss - 0.5 v ~ 2.3 v v 1,4 t stg storage temperature -55 to +150 c 1, 2 notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability 2. storage temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, please refer to jesd51-2 standard. 3. vdd and vddq must be within 300mv of each other at all times; and vref must be not greater than 0.6 x vddq. when vdd and vddq and vddl are less than 500 mv, vref may be equal to or less than 300 mv. 4. voltage on any input or i/o may not exceed voltage on vddq. ac ?&?dc?recommended?operating?conditions recommended?dc?operating?conditions?(sstl-1.8) symbol parameter rating units notes min. typ. max. vdd supply voltage 1.7 1.8 1.9 v 1 vddl supply voltage for dll 1.7 1.8 1.9 v 5 vddq supply voltage for output 1.7 1.8 1.9 v 1, 5 vref input reference voltage 0.49 x vddq 0.50 x vddq 0.51 x vddq mv 2. 3 vtt termination voltage vref - 0.04 vref vref + 0.04 v 4 notes: 1. there is no specifc device vdd supply voltage requirement for sstl_18 compliance. however under all conditions vddq must be less than or equal to vdd. 2. the value of vref may be selected by the user to provide optimum noise margin in the system. typically the value of vref is expected to be about 0.5 x vddq of the transmitting device and vref is expected to track variations in vddq. 3. peak to peak ac noise on vref may not exceed +/-2 % vref(dc). 4. vtt of transmitting device must track vref of receiving device. 5. vddq tracks with vdd, vddl tracks with vdd. ac parameters are measured with vdd, vddq and vdddl tied together
integrated silicon solution, inc. www.issi.com 7 rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a symbol parameter rating ?(1,2,3) units toper commercial temperature t c = 0 to +85 o c t a = 0 to +70 o c industrial temperature, t c = -40 to +95 o c automotive temperature (a1) t a = -40 to +85 o c automotive temperature (a2) t c = -40 to +105 o c t a = -40 to +105 o c operating? temperature ?condition odt?dc?electrical?characteristics parameter/condition ? symbol min nom max? units? notes r tt effective impedance value for emrs(1)[a6,a2]=0,1; 75 r tt 1(eff) 60 75 90 1 r tt effective impedance value for emrs(1)[a6,a2]=1,0; 150 r tt 2(eff) 120 150 180 1 r tt effective impedance value for emrs(1)[a6,a2]=1,1; 50 r tt 3(eff) 40 50 60 1 deviation of vm with respect to vddq/2 vm - 6 + 6 % 1 notes: 1. test condition for r tt measurements measurement defnition for r tt (eff): apply vih (ac) and vil (ac) to test pin separately, then measure current i(vih (ac)) and i( vil (ac)) respectively. vih (ac), vil (ac), and vddq values defned in sstl_18 r tt (eff) v ih (ac) - v il (ac) i(v ih (ac)) - i(v il (ac)) measurement defnition for vm: measure voltage (vm) at test pin (midpoint) with no load. vm = [(2 x vm / vddq) - 1] x 100% notes: 1. t c = operating case temperature at center of package 2. t a = operating ambient temperature immediately above package center. 3. both temperature specifcations must be met. package substrate theta-ja?? (airfow ?=?0m/s) theta-ja? (airfow ?=?1m/s) theta-ja? (airfow ?=?2m/s) theta-jc units 126-ball wbga 4-layer 29.47 28.61 27.93 2.42 c/w thermal?resistance
8 integrated silicon solution, inc. www.issi.com rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a input?dc?logic? level symbol? parameter min. max. units notes vih(dc) dc input logic high vref + 0.125 vddq + 0.3 v vil(dc) dc input logic low - 0.3 vref - 0.125 v input? ac?logic? level symbol parameter ddr2-400, ?ddr2-533 units notes min. max. vih (ac) ac input logic high vref + 0.250 vddq + vpeak v 1 vil (ac) ac input logic low vssq - vpeak vref - 0.250 v 1 ac ?input? test ?conditions symbol condition value units notes vref input reference voltage 0.5 x vddq v 1 vswing(max) input signal maximum peak to peak swing 1.0 v 1 slew input signal minimum slew rate 1.0 v/ns 2, 3 notes: 1. refer to overshoot/undershoot specifcations for vpeak value: maximum peak amplitude allowed for overshoot and undershoot. notes: 1. input waveform timing is referenced to the input signal crossing through the vih/il(ac) level applied to the device under test. 2. the input signal minimum slew rate is to be maintained over the range from vref to vih(ac) min for rising edges and the range from vref to vil(ac) max for falling edges as shown in the below fgure. 3. ac timings are referenced with input waveforms switching from vil(ac) to vih(ac) on the positive transitions and vih(ac) to vil(ac) on the negative transitions. ac ?input?test?signal? waveform v dd q v ih(ac) mi n v ih(dc) mi n v re f v il(dc ) max v il(ac ) max v ss v swing(max) d tr d tf v ref - v il (ac) max dtf falling slew = rising slew = v ih(ac) min - v ref dtr
integrated silicon solution, inc. www.issi.com 9 rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a differential ?input? ac?logic? level symbol parameter min. max. units notes vid (ac) ac differential input voltage 0.5 vddq v 1,3 vix (ac) ac differential crosspoint voltage 0.5 x vddq - 0.175 0.5 x vddq + 0.175 v 2 notes: 1. vid(ac) specifes the input differential voltage |vtr -vcp | required for switching, where vtr is the true input signal (such as ck, dqs and vcp is the complementary input signal (such as ck or dqs). the minimum value is equal to vih(ac) - vil(ac). 2. the typical value of vix(ac) is expected to be about 0.5 x vddq of the transmitting device and vix(ac) is expected to track variations in vddq. vix(ac) indicates the voltage at which differential input signals must cross. 3. refer to overshoot/undershoot specifcations for vpeak value: maximum peak amplitude allowed for overshoot and undershoot. differential ?signal? levels v dd q crossing poi n t v ssq v tr v cp v id v ix or v ox differential ? ac?output? parameters symbol parameter min. max. units notes vox (ac) ac differential crosspoint voltage 0.5 x vddq - 0.125 0.5 x vddq + 0.125 v 1 note: 1. the typical value of vox(ac) is expected to be about 0.5 x vddq of the transmitting device and vox(ac) is expected to track variations in vddq. vox(ac) indicates the voltage at which differential output signals must cross.
10 integrated silicon solution, inc. www.issi.com rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a o versh oot/undersh oot?s pecification ac ? overshoot/undershoot?specifcation? for? address?and? control?pins parameter specifcation ddr2-400 ddr2-533 maximum peak amplitude allowed for overshoot area 0.5v 0.5v maximum peak amplitude allowed for undershoot area 0.5v 0.5v maximum overshoot area above vdd (see fgure below) 1.33 v-ns 1.0 v-ns maximum undershoot area below vss (see fgure below) 1.33 v-ns 1.0 v-ns overshoo t a re a maximum amplitude v dd undershoot area maximu m a mplitude v ss vo lt s (v) ti me (ns) overshoo t a re a maximum amplitud e v ddq undershoo t a re a maximu m a mplitude v ssq vo lt s (v ) ti me (ns) ac overshoot and undershoot defnition for address and control pins ac ? overshoot/undershoot?specifcation? for? clock, ?data, ? strobe, ?and?mask?pins: dq, ?dqs, ?dqs, ?dm, ?ck, ?ck parameter specifcation ddr2-400 ddr2-533 maximum peak amplitude allowed for overshoot area 0.5v 0.5v maximum peak amplitude allowed for undershoot area 0.5v 0.5v maximum overshoot area above vddq (see fgure below) 0.38 v-ns 0.28 v-ns maximum undershoot area below vssq (see fgure below) 0.38 v-ns 0.28 v-ns ac overshoot and undershoot defnition for clock, data, strobe, and mask pins
integrated silicon solution, inc. www.issi.com 11 rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a output? buffer?characteristics output? ac? test ?conditions symbol parameter sstl_18 units notes votr output timing measurement reference level 0.5 x vddq v 1 output?dc?current?drive symbol parameter sstl_18 units notes ioh(dc) output minimum source dc current - 13.4 ma 1, 3, 4 iol(dc) output minimum sink dc current 13.4 ma 2, 3, 4 notes: 1. vddq = 1.7 v; vout = 1420 mv. (vout - vddq)/ioh must be less than 21 for values of vout between vddq and vddq - 280 mv. 2. vddq = 1.7 v; vout = 280 mv. vout/iol must be less than 21 for values of vout between 0 v and 280 mv. 3. the dc value of vref applied to the receiving device is set to vtt 4. the values of ioh(dc) and iol(dc) are based on the conditions given in notes 1 and 2. they are used to test device drive current capability to ensure vih min plus a noise margin and vil max minus a noise margin are delivered to an sstl_18 receiver. the actual current values are derived by shifting the desired driver operating point (see section 3.3 of jesd8-15a) along a 21 load line to defne a convenient driver cur- rent for measurement. ocd?default?characteristics description parameter min nom max unit notes output impedance see full strength default driver characteristics 1 output impedance step size for ocd calibration 0 1.5 6 pull-up and pull-down mismatch 0 4 1,2,3 output slew rate sout 1.5 5 v/ns 1,4,5,7,8,9 notes: 1. absolute specifcations (toper; vdd = +1.8v 0.1v, vddq = +1.8v 0.1v). dram i/o specifcations for timing, voltage, and slew rate are no longer applicable if ocd is changed from default settings. 2. impedance measurement condition for output source dc current: vddq = 1.7 v; vout = 1420 mv; (voutvddq)/ioh must be less than 23.4 for values of vout between vddq and vddq - 280 mv. impedance measurement condition for output sink dc current: vddq = 1.7 v; vout = 280 mv; vout/iol must be less than 23.4 for values of vout between 0 v and 280 mv. 3. mismatch is absolute value between pull-up and pull-down, both are measured at same temperature and voltage. 4. slew rate measured from vil(ac) to vih(ac). 5. the absolute value of the slew rate as measured from dc to dc is equal to or greater than the slew rate as measured from ac to ac. this is guaranteed by design and characterization. 6. this represents the step size when the ocd is near 18 at nominal conditions across all process corners/variations and represents only the dram uncertainty. a 0 value (no calibration) can only be achieved if the ocd impedance is 18 +/-0.75 under nominal conditions. 7. dram output slew rate specifcation applies to 400 mt/s and 533 mt/s speed bins. 8. timing skew due to dram output slew rate mis-match between dqs / dqs and associated dqs is included in tdqsq and tqhs specifcation. 9. ddr2 sdram output slew rate test load is defned in guideline 3 of the ac timing specifcation table.
12 integrated silicon solution, inc. www.issi.com rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a symbol ? conditions ? -37c -5b units ddr2- 533c? ddr2- 400b? idd0 operating one bank active-precharge current; tck = tck(idd), trc = trc(idd), tras = trasmin(idd); cke is high, cs is high between valid commands; 50% of address bus inputs are switching; data bus inputs are switching 130 120 ma idd1 operating one bank active-read-precharge current; iout = 0ma; bl = 4, cl = cl(idd), al = 0; tck = tck(idd), trc = trc (idd), tras = trasmin(idd), trcd = trcd(idd); cke is high, cs is high between valid commands; 50% of address bus inputs are switching; data pattern is same as idd4w 165 150 ma idd2p precharge power-down current; all banks idle; tck = tck(idd); cke is low; other control and address bus inputs are stable; 8 8 ma data bus inputs are floating idd2q precharge quiet standby current; all banks idle; tck = tck(idd); cke is high, cs is high; other control and address bus inputs are stable; 55 45 ma data bus inputs are floating idd2n precharge standby current; all banks idle; tck = tck(idd); cke is high, cs is high; other control and 50% of address bus inputs are switching; data bus inputs are switching 70 60 ma idd3p active power-down current; all banks open; tck = tck(idd); cke is low; other control and address bus inputs are stable; 20 15 ma data bus inputs are floating idd3n active standby current; all banks open; tck = tck(idd), tras = trasmax(idd), trp = trp(idd); cke is high, cs is high between valid commands; other control and 50% of address bus inputs are switching; data bus inputs are switching 60 50 ma idd4w operating burst write current; all banks open, continuous burst writes; bl = 4, cl = cl(idd), al = 0; tck = tck(idd), tras = trasmax(idd), trp = trp(idd); cke is high, cs is high between valid commands; 50% of address bus inputs are switching; data bus inputs are switching 280 210 ma idd?specifcations?&? test ?conditions
integrated silicon solution, inc. www.issi.com 13 rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a symbol ? conditions ? -37c -5b units ddr2- 533c? ddr2- 400b? idd4r operating burst read current; all banks open, continuous burst reads, iout = 0 ma; bl = 4, cl = cl(idd), al = 0; tck = tck(idd), tras = trasmax(idd), trp = trp(idd); cke is high, cs is high between valid commands; 50% of address bus inputs are switching; data pattern is same as idd4w 240 180 ma idd5b burst refresh current; tck = tck(idd); refresh command at every trfc(idd) interval; cke is high, cs is high between valid commands; other control and 50% of address bus inputs are switching; data bus inputs are switching reduced page (8k) 170 150 ma standard page (4k) 265 245 idd6 self refresh current; ck and ck at 0 v; cke 0.2 v; other control and address bus inputs are floating; 6 6 ma data bus inputs are floating idd7 operating bank interleave read current; all bank interleaving reads, iout = 0ma; bl = 4, cl = cl(idd), al = trcd(idd) - 1 x tck(idd); tck = tck(idd), trc = trc(idd), trrd = trrd(idd), trcd = 1 x tck(idd); cke is high, cs is high between valid commands; address bus inputs are stable during deselects; 450 430 ma idd?specifcations?&? test ?conditions? (continued) notes: 1. idd specifcations are tested after the device is properly initialized 2. input slew rate is specifed by ac parametric test condition 3. idd parameters are specifed with odt disabled. 4. data bus consists of dq, dm, dqs and dqs. idd values must be met with all combinations of emr(1) bits 10 and 11. 5. defnitions for idd low = vin vilac(max) high = vin vihac(min) stable = inputs stable at a high or low level floating = inputs at vref = vddq/2 switching = inputs changing between high and low every other clock cycle (once per two clocks) for address and control signals, and inputs changing between high and low every other data transfer (once per clock) for dq signals not including masks or strobes.
14 integrated silicon solution, inc. www.issi.com rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a idd?testing? parameters speed ddr2-533 ddr2-400 units bin(cl-trcd-trp) 4-4-4 3-3-3 cl(idd) 4 3 tck trcd(idd) 15 15 ns trc(idd) 60 55 ns trrd(idd) 7.5 7.5 ns tck(idd) 3.75 5 ns trasmin(idd) 45 40 ns trasmax(idd) 70 70 ms trp(idd) 15 15 ns trfc(idd) 75 75 ns
integrated silicon solution, inc. www.issi.com 15 rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a input/output?capacitance parameter symbol ddr2-400 ddr2-533 units min. max. input capacitance, ck and ck cck 1.0 2.0 pf input capacitance delta, ck and ck cdck C 0.25 pf input capacitance, all other input-only pins ci 1.0 2.0 pf input capacitance delta, all other input-only pins cdi C 0.25 pf input/output capacitance, dq, dm, dqs, dqs cio 2.5 4.0 pf input/output capacitance delta, dq, dm, dqs, dqs cdio C 0.5 pf electrical?characteristics?&? ac? timing?specifcations refresh? parameters? (toper; vddq = 1.8 v +/- 0.1 v; vdd = 1.8 v +/- 0.1 v) parameter symbol units notes refresh to active/refresh command time trfc 75 ns 1 average periodic refresh interval trefi -40 o c tc < 0 o c 7.8 ms 1,2 0 o c tc 85 o c 7.8 ms 1 85 o c < tc 95 o c 3.9 ms 1,2 95 o c < tc 105 o c 3.9 ms 1,2,3 notes: 1. if refresh timing is violated, data corruption may occur and the data must be re-written with valid data before a valid read can be executed. 2. specifed for automotive and industrial grade only; not applicable for commercial grade. t oper may not be violated. 3. specifed for automotive grade (a2) only; not applicable for any other grade. toper may not be violated. key ? timing? parameters? by?speed?grade -37c -5b speed bin (jedec) ddr2-533c ddr2-400b cl-trcd-trp 4-4-4 3-3-3 trcd 15 15 trp 15 15 trc 60 55 tras 45 40 tck(avg)@cl=3 5 5 tck(avg)@cl=4 3.75 5 tck(avg)@cl=5 3.75 5 tck(avg)@cl=6 3.75 5
16 integrated silicon solution, inc. www.issi.com rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a timing? parameters? by?speed?grade?(ddr2-400?and?ddr2-533) (for information related to the entries in this table, refer to both the guidelines and the specifc notes following this table.) parameter symbol ddr2-400 ddr2-533 units notes min. max. min. max clock cycle time, cl=x tck 5 8 3.75 8 ns 15 ck high pulse width tch 0.45 0.55 0.45 0.55 tck ck low pulse width tcl 0.45 0.55 0.45 0.55 tck dqs latching rising transitions to associated clock edges tdqss - 0.25 0.25 - 0.25 0.25 tck dqs falling edge to ck setup time tdss 0.2 C 0.2 C tck dqs falling edge hold time from ck tdsh 0.2 C 0.2 C tck dqs input high pulse width tdqsh 0.35 C 0.35 C tck dqs input low pulse width tdqsl 0.35 C 0.35 C tck write preamble twpre 0.35 C 0.35 C tck write postamble twpst 0.4 0.6 0.4 0.6 tck 10 address and control input setup time tisa 600 C 500 C ps 5, 7, 9, 22, 29 address and control input hold time tiha 600 C 500 C ps 5, 7, 9, 23, 29 address and control input setup time tis(base) 350 C 250 C ps 5, 7, 9, 22, 29 address and control input hold time tih(base) 475 C 375 C ps 5, 7, 9, 23, 29 control & address input pulse width for each input tipw 0.6 C 0.6 C tck dq and dm input setup time tdsa 400 C 350 C ps 6, 7, 8, 20, 28, 31 dq and dm input hold time tdha 400 C 350 C ps 6, 7, 8, 21, 28, 31 dq and dm input setup time (differential strobe) tds(base) 150 C 100 C ps 6, 7, 8, 20, 28, 31 dq and dm input hold time (differential strobe) tdh(base) 275 C 225 C ps 6, 7, 8, 21, 28, 31 dq and dm input setup time (single-ended strobe) tds1(base) 25 C - 25 C ps 6, 7, 8, 25 dq and dm input hold time (single-ended strobe) tdh1(base) 25 C - 25 C ps 6, 7, 8, 26 dq and dm input pulse width for each input tdipw 0.35 C 0.35 C tck dq output access time from ck/ck tac - 600 + 600 - 500 + 500 ps dqs output access time from ck/ ck tdqsck - 500 + 500 - 450 + 450 ps data-out high-impedance time from ck/ ck thz C tac max C tac max ps 18 dqs(dqs) low-impedance time from ck/ ck tlz(dqs) tac min tac max tac min tac max ps 18 dq low-impedance time from ck/ ck tlz(dq) 2 x tac min tac max 2 x tac min tac max ps 18 dqs-dq skew for dqs and associated dq signals tdqsq C 350 C 300 ps 13 ck half pulse width thp min (tcl, tch) C min (tcl, tch) C ps 11,12 dq hold skew factor tqhs C 450 C 400 ps 12 dq/dqs output hold time from dqs tqh thp - tqhs C thp - tqhs C ps read preamble trpre 0.9 1.1 0.9 1.1 tck 19 read postamble trpst 0.4 0.6 0.4 0.6 tck 19
integrated silicon solution, inc. www.issi.com 17 rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a timing? parameters? by?speed?grade?(ddr2-400?and?ddr2-533)?cont'd (for information related to the entries in this table, refer to both the guidelines and the specifc notes following this table.) parameter symbol ddr2-400 ddr2-533 units notes min. max. min. max. active to active command period trrd 7.5 C 7.5 C ns 4 cas to cas command delay tccd 2 C 2 C tck write recovery time twr 15 C 15 C ns auto precharge write recovery + precharge time tdal wr + trp C wr + trp C tck 14 internal write to read command delay twtr 10 C 7.5 C ns 24 internal read to precharge command delay trtp 7.5 C 7.5 C ns 3 cke minimum pulse width (high and low pulse width) tcke 3 C 3 C tck 27 exit self refresh to a non-read command txsnr trfc + 10 C trfc + 10 C ns exit self refresh to a read command txsrd 200 C 200 C tck exit precharge power down to any non- read command txp 2 C 2 C tck exit active power down to read command txard 2 C 2 C tck 1 exit active power down to read command (slow exit, lower power) txards 6 - al C 6 - al C tck 1,2 odt turn-on delay taond 2 2 2 2 tck 16 odt turn-on taon tac(min) tac(max)+1 tac(min) tac (max)+1 ns 16 odt turn-on (power-down mode) taonpd tac(min)+2 2 x tck + tac(max)+1 tac(min) + 2 2 x tck + tac(max)+1 ns odt turn-off delay taofd 2.5 2.5 2.5 2.5 tck 17, 44 odt turn-off taof tac(min) tac(max) + 0.6 tac(min) tac(max) + 0.6 ns 17, 44 odt turn-off (power-down mode) taofpd tac(min)+2 2.5 x tck + tac(max)+1 tac(min)+2 2.5 x tck+ tac(max)+1 ns odt to power down entry latency tanpd 3 C 3 C tck odt power down exit latency taxpd 8 C 8 C tck mode register set command cycle time tmrd 2 C 2 C tck mrs command to odt update delay tmod 0 12 0 12 ns ocd drive mode output delay toit 0 12 0 12 ns minimum time clocks remains on after cke asynchronously drops low tdelay tis+tck+tih C tis+tck+tih C ns 15
18 integrated silicon solution, inc. www.issi.com rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a guidelines? for? ac? parameters 1. ?ddr2?sdram? ac? timing? reference?load figure "ac timing reference load" represents the timing reference load used in defning the relevant timing parameters of the part. it is not intended to be either a precise representation of the typical system environment or a depiction of the actual load presented by a production tester. system designers will use ibis or other simulation tools to correlate the timing reference load to a system environment. manufacturers correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). vddq dut dq dqs dqs output v tt = v ddq /2 25? ti ming referenc e point figure - ac timing reference load the output timing reference voltage level for single ended signals is the crosspoint with vtt. the output timing reference voltage level for differential signals is the crosspoint of the true (e.g. dqs) and the complement (e.g. dqs) signal. 2. ? slew?rate?measurement? levels a) output slew rate for falling and rising edges is measured between vtt - 250 mv and vtt + 250 mv for single ended signals. for differential signals (e.g. dqs - 10) output slew rate is measured between dqs - 10 = - 500 mv and dqs - 10 = + 500 mv. output slew rate is guaranteed by design, but is not necessarily tested on each device. b) input slew rate for single ended signals is measured from vref(dc) to vih(ac),min for rising edges and from vref(dc) to vil(ac),max for falling edges. for differential signals (e.g. ck - 9/) slew rate for rising edges is measured from ck - 9/ = - 250 mv to ck - 9/ = + 500 mv (+ 250 mv to - 500 mv for falling edges). c) vid is the magnitude of the difference between the input voltage on ck and the input voltage on ck, or between dqs and 10 for differential strobe. 3. ?ddr2?sdram?output? slew?rate?test?load output slew rate is characterized under the test conditions as shown in figure "slew rate test load". 4. ? differential?data? strobe ddr2 sdram pin timings are specifed for either single ended mode or differential mode depending on the setting of the emrs enable dqs mode bit; timing advantages of differential mode are realized in system design. the method by which the ddr2 sdram pin timings are measured is mode dependent. in single ended mode, timing relationships are measured relative to the rising or falling edges of dqs crossing at vref. in differential mode, these timing vddq du t dq dq s, dq s output v tt = v ddq /2 25? te st point figure - slew rate test loa d relationships are measured relative to the crosspoint of dqs and its complement, 10. this distinction in timing methods is guaranteed by design and characterization. note that when differential data strobe mode is disabled via the emrs, the complementary pin, 10, must be tied externally to vss through a 20 to 10 k resistor to insure proper operation.
integrated silicon solution, inc. www.issi.com 19 rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a 5. ac timings are for linear signal transitions. see specifc notes on derating for other signal transitions. 6. all voltages are referenced to vss. 7. ?these parameters guarantee device behavior, but they are not necessarily tested on each device they may be guaranteed by device design or tester correlation. 8. tests for ac timing, idd, and electrical (ac and dc) characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifcations and device operation are guaranteed for the full voltage range specifed. ? specifc?notes? for?dedicated? ac? parameters 1. user can choose which active power down exit timing to use via mode register set [a12]. txard is expected to be used for fast active power down exit timing. txards is expected to be used for slow active power down exit timing. 2. al = additive latency. 3. this is a minimum requirement. minimum read to precharge timing is al + bl / 2 provided that the trtp and tras(min) have been satisfed. 4. a minimum of two clocks (2 x tck or 2 x nck) is required irrespective of operating frequency. 5. timings are specifed with command/address input slew rate of 1.0 v/ns. see specifc notes on derating for other slew rate values. 6. timings are specifed with dqs, dm, and dqss (dqs in single ended mode) input slew rate of 1.0v/ns. see specifc notes on derating for other slew rate values. t ds t ds t dh t wp re t w pst t dqsh t dq sl dqs dqs d dmi n dqs/ dq dm t dh dmi n dmi n dmi n d d d dqs v il (ac) v ih (ac ) v il (ac) v ih (a c) v il (dc) v ih (d c) v il (dc) v ih (d c) t ch t cl ck ck ck/ck dqs/dqs dq dqs dqs t r pst q t rpre t dq sq ma x t qh t qh t dqsq ma x q q q data?input?(write)? timing data?output?(read)? timing
20 integrated silicon solution, inc. www.issi.com rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a 7. ?timings are specifed with ck/ck differential slew rate of 2.0 v/ns. timings are guaranteed for dqs signals with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. see specifc notes on derating for other slew rate values. 8. data setup and hold time derating (t ds , t dh ). d tds, dtdh derating values for ddr2-400, ddr2-553 (all units in ps; the note applies to the entire table) dqs, dqs differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns dtds dtdh dtds dtdh dtds dtdh dtds dtdh dtds dtdh dtds dtdh dtds dtdh dtds dtdh dtds dtdh dq slew rate v/ns 2.0 125 45 125 45 125 45 - - - - - - - - - - - - 1.5 83 21 83 21 83 21 95 33 - - - - - - - - - - 1.0 0 0 0 0 0 0 12 12 24 24 - - - - - - - - 0.9 - - -11 -14 -11 -14 1 -2 13 10 25 22 - - - - - - 0.8 - - - - -25 -31 -13 -19 -1 -7 11 5 23 17 - - - - 0.7 - - - - - - -31 -42 -19 -30 -7 -18 5 -6 17 6 - - 0.6 - - - - - - - - -43 -59 -31 -47 -19 -35 -7 -23 5 -11 0.5 - - - - - - - - - - -74 -89 -62 -77 -50 -65 -38 -53 0.4 - - - - - - - - - - - - -127 -140 -115 -128 -103 -116 ddr2-400/533?tds/tdh?derating?with? differential?data? strobe
integrated silicon solution, inc. www.issi.com 21 rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a ddr2-400/533?tds1/tdh1?derating?with?single-ended?data? strobe for all input signals the total tds (setup time) and tdh (hold time) required is calculated by adding the data sheet tds(base) and tdh(base) value to the dtds and dtdh derating value respectively. example: tds (total setup time) = tds(base) + d tds. setup (tds) nominal slew rate for a rising signal is defned as the slew rate between the last crossing of vref(dc) and the frst crossing of vih(ac)min. setup (tds) nominal slew rate for a falling signal is defned as the slew rate between the last crossing of vref(dc) and the frst crossing of vil(ac)max. if the actual signal is always earlier than the nominal slew rate line between shaded vref(dc) to ac region, use nominal slew rate for derating value. if the actual signal is later than the nominal slew rate line anywhere between shaded vref(dc) to ac region, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value. hold (tdh) nominal slew rate for a rising signal is defned as the slew rate between the last crossing of vil(dc)max and the frst crossing of vref(dc). hold (tdh) nominal slew rate for a falling signal is defned as the slew rate between the last crossing of vih(dc)min and the frst crossing of vref(dc). if the actual signal is always later than the nominal slew rate line between shaded dc level to vref(dc) region, use nominal slew rate for derating value. if the actual signal is earlier than the nominal slew rate line anywhere between shaded dc to vref(dc) region, the slew rate of a tangent line to the actual signal from the dc level to vref(dc) level is used for derating value. although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached vih/ il(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach vih/il(ac). for slew rates in between the values listed in the "data setup and hold time derating" table, the derating values may obtained by linear interpolation. these values are typically not subject to production test. they are verifed by design and characterization. dtds1, dtdh1 derating values for ddr2-400, ddr2-533 (all units in ps; the note applies to the entire table) dqs, single-ended slew rate 2.0 v/ns 1.5 v/ns 1.0 v/ns 0.9 v/ns 0.8 v/ns 0.7 v/ns 0.6 v/ns 0.5 v/ns 0.4 v/ns d tds1 d tdh1 d tds1 d tdh1 d tds1 dtdh d tds1 d tdh1 d tds1 d tdh1 d tds1 d tdh1 d tds1 d tdh1 d tds1 d tdh1 d tds1 d tdh1 dq slew rate v/ns 2.0 188 167 145 125 63 - - - - - - - - - - - - - 1.5 146 167 125 125 83 42 81 43 - - - - - - - - - - 1.0 63 125 42 83 0 0 -2 1 -7 -13 - - - - - - - - 0.9 - - 31 69 -11 -14 -13 -13 -18 -27 -29 -45 - - - - - - 0.8 - - - - -25 -31 -27 -30 -32 -44 -43 -62 -60 -86 - - - - 0.7 - - - - - - -45 -53 -50 -67 -61 -85 -78 -109 -108 -152 - - 0.6 - - - - - - - - -74 -96 -85 -114 -102 -138 -132 -181 -183 -246 0.5 - - - - - - - - - - -128 -156 -145 -180 -175 -223 -226 -288 0.4 - - - - - - - - - - - - -210 -243 -240 -286 -291 -351
22 integrated silicon solution, inc. www.issi.com rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a 9. input setup and hold time derating (tis, tih) tis, tih derating values for ddr2-400, ddr2-533 ck, /ck differential slew rate 2.0 v/ns 1.5 v/ns 1.0 v/ns units dtis dtih dtis dtih dtis dtih command/ address slew rate (v/ns) 4.0 187 94 217 124 247 154 ps 3.5 179 89 209 119 239 149 ps 3 167 83 197 113 227 143 ps 2.5 150 75 180 105 210 135 ps 2.0 125 45 155 75 185 105 ps 1.5 83 21 113 51 143 81 ps 1.0 0 0 30 30 60 60 ps 0.9 -11 -14 19 16 49 46 ps 0.8 -25 -31 5 -1 35 29 ps 0.7 -43 -54 -13 -24 17 6 ps 0.6 -67 -83 -37 -53 -7 -23 ps 0.5 -110 -125 -80 -95 -50 -65 ps 0.4 -175 -188 -145 -158 -115 -128 ps 0.3 -285 -292 -255 -262 -225 -232 ps 0.25 -350 -375 -320 -345 -290 -315 ps 0.2 -525 -500 -495 -470 -465 -440 ps 0.15 -800 -708 -770 -678 -740 -648 ps 0.1 -1450 -1125 -1420 -1095 -1390 -1065 ps for all input signals the total tis (setup time) and tih (hold time) required is calculated by adding the data sheet tis(base) and tih(base) value to the dtis and dtih derating value respectively. example: tis (total setup time) = tis(base) + dtis setup (tis) nominal slew rate for a rising signal is defned as the slew rate between the last crossing of vref(dc) and the frst crossing of vih(ac)min. setup (tis) nominal slew rate for a falling signal is defned as the slew rate between the last crossing of vref(dc) and the frst crossing of vil(ac)max. if the actual signal is always earlier than the nominal slew rate line between shaded vref(dc) to ac region, use nominal slew rate for derating value. if the actual signal is later than the nominal slew rate line anywhere between shaded vref(dc) to ac region, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value. hold (tih) nominal slew rate for a rising signal is defned as the slew rate between the last crossing of vil(dc)max and the frst crossing of vref(dc). hold (tih) nominal slew rate for a falling signal is defned as the slew rate between the last crossing of vih(dc)min and the frst crossing of vref(dc). if the actual signal is always later than the nominal slew rate line between shaded dc to vref(dc) region, use nominal slew rate for derating value. if the actual signal is earlier than the nominal slew rate line anywhere between shaded dc to vref(dc) region, the slew rate of a tangent line to the actual signal from the dc level to vref(dc) level is used for derating value. although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached vih/ il(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach vih/il(ac). for slew rates in between the values listed in the "input setup and hold time derating" table, the derating values may obtained by linear interpolation. these values are typically not subject to production test. they are verifed by design and characterization.
integrated silicon solution, inc. www.issi.com 23 rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a 10. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 11. min ( tcl, tch) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specifcation limits for tcl and tch). for example, tcl and tch are = 50% of the period, less the half period jitter ( tjit(hp)) of the clock source, and less the half period jitter due to crosstalk ( tjit(crosstalk)) into the clock traces. 12. tqh = thp C tqhs, where: thp = minimum half clock period for any given cycle and is defned by clock high or clock low (tch, tcl). tqhs accounts for: 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of dqs on one transition followed by the worst case pull-in of dq on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 13. tdqsq: consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between dqs / dqs and associated dq in any given cycle. 14. tdal = wr + ru{ trp[ns] / tck[ns] }, where ru stands for round up. wr refers to the twr parameter stored in the mrs. for trp, if the result of the division is not already an integer, round up to the next highest integer. tck refers to the application clock period. example: for ddr533 at tck = 3.75ns with wr programmed to 4 clocks. tdal = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 15. the clock frequency is allowed to change during selfCrefresh mode or precharge power-down mode. in case of clock frequency change during precharge power-down, a specifc procedure is required as described in section 3.13. 16. odt turn on time min is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measured from taond, which is interpreted differently per speed bin. for ddr2-400/533, taond is 10 ns (= 2 x 5 ns) after the clock edge that registered a frst odt high if tck = 5 ns. 17. odt turn off time min is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from taofd, which is interpreted differently per speed bin. for ddr2- 400/533, taofd is 12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a frst odt low if tck = 5 ns. 18. thz and tlz transitions occur in the same access time as valid data transitions. these parameters are referenced to a specifc voltage level which specifes when the device output is no longer driving (thz), or begins driving (tlz) . one method to calculate the point when device is no longer driving (thz), or begins driving (tlz) is by measuring the signal at two different voltages. the actual voltage measurement points are not critical as long as the calculation is consistent. tlz(dq) refers to tlz of the dqs, and tlz(dqs) refers to tlz of the dqs and dqs, each treated as single- ended signal. 19. trpst end point and trpre begin point are not referenced to a specifc voltage level but specify when the device output is no longer driving (trpst), or begins driving (trpre). one method to calculate these points when the device is no longer driving (trpst), or begins driving (trpre) is by measuring the signal at two different voltages. the actual voltage measurement points are not critical as long as the calculation is consistent.
24 integrated silicon solution, inc. www.issi.com rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a 20. input waveform timing tds with differential data strobe enabled is referenced from the input signal crossing at the vih(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the vil(ac) level to the differential data strobe crosspoint for a falling signal applied to the device under test. dqs, dqs signals must be monotonic between vil(dc)max and vih(dc)min. 21. input waveform timing tdh with differential data strobe enabled is referenced from the differential data strobe crosspoint to the input signal crossing at the vih(dc) level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the vil(dc) level for a rising signal applied to the device under test. dqs, dqs signals must be monotonic between vil(dc)max and vih(dc)min. 22. input waveform timing is referenced from the input signal crossing at the vih(ac) level for a rising signal and vil(ac) for a falling signal applied to the device under test. 23. input waveform timing is referenced from the input signal crossing at the vil(dc) level for a rising signal and vih(dc) for a falling signal applied to the device under test. 24. twtr is at lease two clocks (2 x tck or 2 x nck) independent of operation frequency. 25. input waveform timing with single-ended data strobe enabled, is referenced from the input signal crossing at the vih(ac) level to the single-ended data strobe crossing vih/l(dc) at the start of its transition for a rising signal, and from the input signal crossing at the vil(ac) level to the single-ended data strobe crossing vih/l(dc) at the start of its transition for a falling signal applied to the device under test. the dqs signal must be monotonic between vil(dc)max and vih(dc)min. 26. input waveform timing with single-ended data strobe enabled, is referenced from the input signal crossing at the vih(dc) level to the single-ended data strobe crossing vih/l(ac) at the end of its transition for a rising signal, and from the input signal crossing at the vil(dc) level to the single-ended data strobe crossing vih/l(ac) at the end of its transition for a falling signal applied to the device under test. the dqs signal must be monotonic between vil(dc)max and vih(dc)min. 27. tckemin of 3 clocks means cke must be registered on three consecutive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. thus, after any cke transition, cke may not transition from its valid level during the time period of tis + 2 x tck + tih. 28. if tds or tdh is violated, data corruption may occur and the data must be re-written with valid data before a valid read can be executed. 29. these parameters are measured from a command/address signal (cke, cs, ras, cas, we, odt, ba0, a0, a1, etc.) transition edge to its respective clock signal (ck/ck) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit(per), tjit(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. that is, these parameters should be met whether clock jitter is present or not. 30. these parameters are measured from a data strobe signal (dqs/dqs) crossing to its respective clock signal (ck/ ck) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit(per), tjit(cc), etc.), as these are relative to the clock signal crossing. that is, these parameters should be met whether clock jitter is present or not. 31. these parameters are measured from a data signal (dm, dq0, dq1, etc.) transition edge to its respective data strobe signal (dqs/ dqs) crossing. 32. for these parameters, the ddr2 sdram device is characterized and verifed to support tnparam = ru{tparam / tck(avg)}, which is in clock cycles, assuming all input clock jitter specifcations are satisfed. for example, the device will support tnrp = ru{trp / tck(avg)}, which is in clock cycles, if all input clock jitter specifcations are met. this means: for ddr2-667 5-5-5, of which trp = 15ns, the device will support tnrp = ru{trp / tck(avg)} = 5, i.e. as long as the input clock jitter specifcations are met, precharge command at tm and active command at tm+5 is valid even if (tm+5 - tm) is less than 15ns due to input clock jitter.
integrated silicon solution, inc. www.issi.com 25 rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a 33. tdal [nck] = wr [nck] + tnrp [nck] = wr + ru {trp [ps] / tck(avg) [ps] }, where wr is the value programmed in the mode register set. 34. new units, tck(avg) and nck, are introduced in ddr2-667 and ddr2-800. unit tck(avg) represents the actual tck(avg) of the input clock under operation. unit nck represents one clock cycle of the input clock, counting the actual clock edges. note that in ddr2-400 and ddr2-533, tck is used for both concepts. ex) txp = 2 [nck] means; if power down exit is registered at tm, an active command may be registered at tm+2, even if (tm+2 - tm) is 2 x tck(avg) + terr(2per),min. 35. input clock jitter spec parameter. these parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to ddr2-667 and ddr2-800 only. the jitter specifed is a random jitter meeting a gaussian distribution. parameter symbol ddr2-800 units min max clock period jitter tjit(per) -100 100 ps clock period jitter during dll locking period tjit(per,lck) -80 80 ps cycle to cycle clock period jitter tjit(cc -200 200 ps cycle to cycle clock period jitter during dll locking period tjit(cc,lck) -160 160 ps cumulative error across 2 cycles terr(2per) -150 150 ps cumulative error across 3 cycles terr(3per) -175 175 ps cumulative error across 4 cycles terr(4per) -200 200 ps cumulative error across 5 cycles terr(5per) -200 200 ps cumulative error across n cycles, n = 6 ... 10, inclusive terr(6- 10per) -300 300 ps cumulative error across n cycles, n = 11 ... 50, inclusive terr(11- 50per) -450 450 ps duty cycle jitter tjit(duty) -100 100 ps
26 integrated silicon solution, inc. www.issi.com rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a 36. these parameters are specifed per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous timing holds at all times. (min and max of spec values are to be used for calculations in the table below.) parameter symbol min max units absolute clock period tck(abs) tck(avg),min + tjit(per),min tck(avg),max + tjit(per),max ps absolute clock high pulse width tch(abs) tch(avg),min x tck(avg),min + tjit(duty),min tch(avg),max x tck(avg),max + tjit(duty),max ps absolute clock low pulse width tcl(abs) tcl(avg),min x tck(avg),min + tjit(duty),min tcl(avg),max x tck(avg),max + tjit(duty),max ps example: for ddr2-667, tch(abs),min = ( 0.48 x 3000 ps ) - 125 ps = 1315 ps 37. thp is the minimum of the absolute half period of the actual input clock. thp is an input parameter but not an input specifcation parameter. it is used in conjunction with tqhs to derive the dram output timing tqh. the value to be used for tqh calculation is determined by the following equation; thp = min ( tch(abs), tcl(abs) ), where, tch(abs) is the minimum of the actual instantaneous clock high time; tcl(abs) is the minimum of the actual instantaneous clock low time; 38. tqhs accounts for: 1) the pulse duration distortion of on-chip clock circuits, which represents how well the actual thp at the input is transferred to the output; and 2) the worst case push-out of dqs on one transition followed by the worst case pull-in of dq on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation of the output drivers 39. tqh = thp C tqhs, where: thp is the minimum of the absolute half period of the actual input clock; and tqhs is the specifcation value under the max column. {the less half-pulse width distortion present, the larger the tqh value is; and the larger the valid data eye will be.} examples: 1) if the system provides thp of 1315 ps into a ddr2-667 sdram, the dram provides tqh of 975 ps minimum. 2) if the system provides thp of 1420 ps into a ddr2-667 sdram, the dram provides tqh of 1080 ps minimum. 40. when the device is operated with input clock jitter, this parameter needs to be derated by the actual terr(6- 10per) of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2-667 sdram has terr(6-10per),min = - 272 ps and terr(6-10per), max = + 293 ps, then tdqsck,min(derated) = tdqsck,min - terr(6-10per),max = - 400 ps - 293 ps = - 693 ps and tdqsck,max(derated) = tdqsck,max - terr(6-10per),min = 400 ps + 272 ps = + 672 ps. similarly, tlz(dq) for ddr2-667 derates to tlz(dq),min(derated) = - 900 ps - 293 ps = - 1193 ps and tlz(dq),max(derated) = 450 ps + 272 ps = + 722 ps. (caution on the min/max usage!)
integrated silicon solution, inc. www.issi.com 27 rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a 41. when the device is operated with input clock jitter, this parameter needs to be derated by the actual tjit(per) of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2-667 sdram has tjit(per),min = - 72 ps and tjit(per),max = + 93 ps, then trpre,min(derated) = trpre,min + tjit(per),min = 0.9 x tck(avg) - 72 ps = + 2178 ps and trpre,max(derated) = trpre,max + tjit(per),max = 1.1 x tck(avg) + 93 ps = + 2843 ps. (caution on the min/max usage!) 42. when the device is operated with input clock jitter, this parameter needs to be derated by the actual tjit(duty) of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2-667 sdram has tjit(duty),min = - 72 ps and tjit(duty),max = + 93 ps, then trpst,min(derated) = trpst,min + tjit(duty),min = 0.4 x tck(avg) - 72 ps = + 928 ps and trpst,max(derated) = trpst,max + tjit(duty),max = 0.6 x tck(avg) + 93 ps = + 1592 ps. (caution on the min/max usage!) 43. when the device is operated with input clock jitter, this parameter needs to be derated by { -tjit(duty),max - terr(6-10per),max } and { - tjit(duty),min - terr(6-10per),min } of the actual input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2-667 sdram has terr(6-10per),min = - 272 ps, terr(6-10per),max = + 293 ps, tjit(duty),min = - 106 ps and tjit(duty),max = + 94 ps, then taof,min(derated) = taof,min + { - tjit(duty), max - terr(6-10per),max } = - 450 ps + { - 94 ps - 293 ps} = - 837 ps and taof,max(derated) = taof,max + { - tjit(duty),min - terr(6-10per),min } = 1050 ps + { 106 ps + 272 ps } = + 1428 ps. (caution on the min/max usage!) 44. for taofd of ddr2-400/533, the 1/2 clock of tck in the 2.5 x tck assumes a tch, input clock high pulse width of 0.5 relative to tck. taof,min and taof,max should each be derated by the same amount as the actual amount of tch offset present at the dram input with respect to 0.5. for example, if an input clock has a worst case tch of 0.45, the taof,min should be derated by subtracting 0.05 x tck from it, whereas if an input clock has a worst case tch of 0.55, the taof,max should be derated by adding 0.05 x tck to it. therefore, we have; taof,min(derated) = tac,min - [0.5 - min(0.5, tch,min)] x tck taof,max(derated) = tac,max + 0.6 + [max(0.5, tch,max) - 0.5] x tck or taof,min(derated) = min(tac,min, tac,min - [0.5 - tch,min] x tck) taof,max(derated) = 0.6 + max(tac,max, tac,max + [tch,max - 0.5] x tck) where tch,min and tch,max are the minimum and maximum of tch actually measured at the dram input balls. 45. for taofd of ddr2-667/800, the 1/2 clock of nck in the 2.5 x nck assumes a tch(avg), average input clock high pulse width of 0.5 relative to tck(avg). taof,min and taof,max should each be derated by the same amount as the actual amount of tch(avg) offset present at the dram input with respect to 0.5. for example, if an input clock has a worst case tch(avg) of 0.48, the taof,min should be derated by subtracting 0.02 x tck(avg) from it, whereas if an input clock has a worst case tch(avg) of 0.52, the taof,max should be derated by adding 0.02 x tck(avg) to it. therefore, we have; taof,min(derated) = tac,min - [0.5 - min(0.5, tch(avg),min)] x tck(avg) taof,max(derated) = tac,max + 0.6 + [max(0.5, tch(avg),max) - 0.5] x tck(avg) or taof,min(derated) = min(tac,min, tac,min - [0.5 - tch(avg),min] x tck(avg)) taof,max(derated) = 0.6 + max(tac,max, tac,max + [tch(avg),max - 0.5] x tck(avg)) where tch(avg),min and tch(avg),max are the minimum and maximum of tch(avg) actually measured at the dram input balls. note that these deratings are in addition to the taof derating per input clock jitter, i.e. tjit(duty) and terr(6-10per). however tac values used in the equations shown above are from the timing parameter table and are not derated. thus the fnal derated values for taof are; taof,min(derated_fnal) = taof,min(derated) + { - tjit(duty),max - terr(6-10per),max } taof,max(derated_fnal) = taof,max(derated) + { - tjit(duty),min - terr(6-10per),min }
28 integrated silicon solution, inc. www.issi.com rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a functional?description power-up ?and?initialization ddr2 sdrams must be powered up and initialized in a predefned manner. operational procedures other than those specifed may result in undefned operation. for ddr2 sdrams, both bits ba0 and ba1 must be decoded for mode/ extended mode register set (mrs/emrs)commands. users must initialize all four mode registers. the registers may be initialized in any order. power-up ?and?initialization?sequence the following sequence is required for power-up and initialization. a) either one of the following sequence is required for power-up. a1) while applying power, attempt to maintain cke below 0.2 x vddq and odt*1 at a low state (all other inputs may be undefned.) the vdd voltage ramp time must be no greater than 200 ms from when vdd ramps from 300 mv to vdd min; and during the vdd voltage ramp, |vdd-vddq| 0.3 volts. once the ramping of the supply voltages is complete (when vddq crosses vddq min), the supply voltage specifcations provided in "recommended dc operating conditions" (sstl_1.8), prevail. - vdd, vddl and vddq are driven from a single power converter output, and - vtt is limited to 0.95v max, and - vref tracks vddq/2, vref must be within +/- 300mv with respect to vddq/2 during supply ramp time. - vddq vref must be met at all times. a2) while applying power, attempt to maintain cke below 0.2 x vddq and odt*1 at a low state, all other inputs may be undefned, voltage levels at i/os and outputs must be less than vddq during voltage ramp time to avoid dram latch-up. during the ramping of the supply voltages, vdd vddl vddq must be maintained and is applicable to both ac and dc levels until the ramping of the supply voltages is complete, which is when vddq crosses vddq min. once the ramping of the supply voltages is complete, the supply voltage specifcations provided in "recommended dc operating conditions" (sstl_1.8), prevail. - apply vdd/vddl before or at the same time as vddq. - vdd/vddl voltage ramp time must be no greater than 200ms from when vdd ramps from 300mv to vdd min - apply vddq before or at the same time as vtt. - the vddq voltage ramp time from when vdd min is achieved on vdd to when vddq min is achieved on vddq must be no greater than 500ms. (note: while vdd is ramping, current may be supplied from vdd through the dram to vddq.) - vref must track vddq/2, vref must be within +/- 300mv with respect to vddq/2 during supply ramp time. - vddq vref must be met at all times. - apply vtt. - the vtt voltage ramp time from when vddq min is achieved on vddq to when vtt min is achieved on vtt must be no greater than 500ms. b) start clock and maintain stable condition. c) for the minimum of 200ms after stable power (vdd, vddl, vddq, vref and vtt are between their minimum and maximum values as stated in "recommended dc operating conditions" (sstl_1.8)) and stable clock (ck, ck), then apply nop or deselect & take cke high. d) wait minimum of 400ns then issue precharge all command. nop or deselect applied during 400 ns period. e) issue an emrs command to emr(2).
integrated silicon solution, inc. www.issi.com 29 rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a power-up ?and?initialization?sequence?(cont'd) f) issue emrs to enable dll. g) issue a mode register set command for dll reset. h) issue a precharge all command. i) issue 2 or more auto-refresh commands. j) issue a mrs command with low to a8 to initialize device operation. (i.e. to program operating parameters without resetting the dll.) k) at least 200 clocks after step h, execute ocd calibration (off chip driver impedance adjustment). if ocd calibration is not used, emrs to emr(1) to set ocd calibration default (a9=a8=a7=high) followed by emrs to emr(1) to exit ocd calibration mode (a9=a8=a7=low) must be issued with other operating parameters of emr(1). l) the ddr2 sdram is now ready for normal operation. initialization?sequence?after? power-up /c k ck ck e co mman d pr e all pr e all em rs mr s r ef re f mr s e mr s emr s any cm d dll enable dll reset oc d default oc d ca l. mode exi t follow ocd fl owchar t 40 0n s trfc tr fc tr p tr p tmrd tmrd tmrd toit min 200 cycl e nop odt tc l tch ti s tis programming ?the?mode?and?extended?mode? registers for application fexibility, burst length, burst type, cas latency, dll reset function, write recovery time (wr) are user defned variables and must be programmed with a mode register set (mrs) command. additionally, dll disable function, driver impedance, additive cas latency, odt (on die termination), single-ended strobe, and ocd (off chip driver impedance adjustment) are also user defned variables and must be programmed with an extended mode register set (emrs) command. contents of the mode register (mr) or extended mode registers can be altered by re-executing the mrs or emrs commands. even if the user chooses to modify only a subset of the mr, emr(1), or emr(2) variables, all variables within the addressed register must be redefned when the mrs or emrs commands are issued. mrs, emrs and reset dll do not affect memory array contents, which means re-initialization including those can be executed at any time after power-up without affecting memory array contents.
30 integrated silicon solution, inc. www.issi.com rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a ddr2?sdram?mode?register?set?(mrs) mode?register?(mr) the mode register stores the data for controlling the various operating modes of the ddr2 sdram. it controls cas latency, burst length, burst sequence, dll reset, wr and power down exit time to make ddr2 sdram useful for various applications. the default value of the mode register is not defned, therefore the mode register must be programmed during initialization for proper operation. the mode register is written by asserting low on cs, ras, cas, we, ba0 and ba1, while controlling the state of address pins a0 - a12. the ddr2 sdram should be in all bank precharge state with cke already high prior to writing into the mode register. the mode register set command cycle time (tmrd) is required to complete the write operation to the mode register. the mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. the mode register is divided into various felds depending on functionality. burst length is defned by a0 - a2 with options of 4 and 8 bit burst lengths. the burst length decodes are compatible with ddr sdram. burst address sequence type is defned by a3, cas latency is defned by a4 - a6. the ddr2 does not support half clock latency mode. a7 is a mode bit and must be set to low for normal mrs operation. a8 is used for dll reset. write recovery time wr is defned by a9 - a11. active power down exit time is defned by a12. refer to the table for specifc codes. notes: 1. for ddr2-400/533, wr (write recovery for autoprecharge) min is determined by tck max and wr max is determined by tck min. wr in clock cycles is calculated by dividing twr (ns) by tck (ns) and rounding up to the next integer (wr[cycles] = ru{ twr[ns] / tck[ns] }, where ru stands for round up). the mode register must be programmed to this value. this is also used with trp to determine tdal. 2. speed option determined. refer to key timing parameter table. address field mode register ba1 0 a12 active power down exit tim e ba0 0 0 fast exit (use txard) 1 slow exit(use txards) a11 a10 a9 wr(cycles) *1 a12 pd 0 0 0 reserved 0 0 1 2 a11 1 wr 0 1 0 3 0 1 1 4 a10 1 1 0 0 5 1 0 1 6 a9 1 1 1 0 reserved 1 1 1 reserved a8 dll a8 dll reset a7 mode a7 tm 0 no 0 normal 1 yes 1 reserved a6 cas latency a6 a5 a4 cas latency a5 0 0 0 reserved 0 0 1 reserved a4 0 1 0 reserved 0 1 1 3 *2 a3 bt 1 0 0 4* 2 1 0 1 5 *2 a2 burst length 1 1 0 6 *2 1 1 1 reserved a1 a3 burst type a2 a1 a0 bl a0 0 sequential 0 1 0 4 1 interleave 0 1 1 8 5 5 3.75 3.75 3.75 5 5 5 t ck (ns) for speed option 2 -5b -37c -- -- -- -- -- --
integrated silicon solution, inc. www.issi.com 31 rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a burst ?mode?operation burst mode operation is used to provide a constant fow of data to memory locations (write cycle), or from memory locations (read cycle). the parameters that defne how the burst mode will operate are burst sequence and burst length. ddr2 sdram supports 4 bit burst and 8 bit burst modes only. for 8 bit burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. the burst type, either sequential or interleaved, is programmable and defned by mr[a3], which is similar to the ddr sdram operation. seamless burst read or write operations are supported. unlike ddr devices, interruption of a burst read or write cycle during bl = 4 mode operation is prohibited. however in case of bl = 8 mode, interruption of a burst read or write operation is limited to two cases, reads interrupted by a read, or writes interrupted by a write. therefore the burst stop command is not supported on ddr2 sdram devices. burst ?length?and?sequence burst length starting address (a1, a0) sequential addressing (decimal) interleave addressing (decimal) 4 0 0 0, 1, 2, 3 0, 1, 2, 3 0 1 1, 2, 3, 0 1, 0, 3, 2 1 0 2, 3, 0, 1 2, 3, 0, 1 1 1 3, 0, 1, 2 3, 2, 1, 0 burst length starting address (a2, a1, a0) sequential addressing (decimal) interleave addressing (decimal) 8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0
32 integrated silicon solution, inc. www.issi.com rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a extended?mode? registers?(emr) extended?mode?register?1?(emr1) the emr(1) stores the data for enabling or disabling the dll, output driver strength, additive latency, odt, dqs disable, ocd program, output buffer disable. the default value of the emr(1) is not defned, therefore the emr(1) must be programmed during initialization for proper operation. the emr(1) is written by asserting low on cs, ras, cas, we, high on ba0 and low on ba1, while controlling the states of address pins a0 - a12. the ddr2 sdram should be in all bank precharge with cke already high prior to writing into the emr(1). the mode register set command cycle time (tmrd) must be satisfed to complete the write operation to the emr(1). emr(1) contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. dll? enable/disable the dll must be enabled for normal operation. dll enable is required during power-up and initialization, and upon returning to normal operation after having the dll disabled. the dll is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. any time the dll is enabled (and subsequently reset), 200 clock cycles must occur before a read command can be issued to allow time for the internal clock to be synchronized with the external clock. failing to wait for synchronization to occur may result in a violation of the tac or tdqsck parameters.
integrated silicon solution, inc. www.issi.com 33 rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a emr(1) address field mode register ba1 0 a12 *4 qoff ba0 1 0 output buffer enabled 1 ouput buffer disabled a12 *4 qoff a11 *1 0 a10 dqs 0 enable a10 dqs 1 disable a9 ocd program a9 a8 a7 ocd calibration program 0 0 0 ocd calibration mode exit; maintain setting a8 0 0 1 drive(1) 0 1 0 drive(0) a7 1 0 0 adjust mode *2 1 1 1 ocd calibration default *3 a6 rtt a5 a4 a3 additive latency a6 a2 rtt(nominal) a5 additive latency 0 0 0 0 0 0 odt disabled 0 0 1 1 0 1 75 ohm a4 0 1 0 2 1 0 150 ohm 0 1 1 3 1 1 50 ohm a3 1 0 0 4 1 0 1 5 a2 rtt 1 1 0 reserved 1 1 1 reserved a1 d.i.c a1 output drive impedance control a0 dll enable a0 dll 0 full strength 0 enable 1 reduced strength 1 disable notes: 1. a11 is reserved for future use and must be set to 0 when programming the emr(1). 2. when adjust mode is issued, al from previously set value must be applied. 3. after setting to default, ocd calibration mode needs to be exited by setting a9-a7 to 000. 4. output disabled - dqs, dqss, dqss. this feature is used in conjunction with dimm idd measurements when iddq is not desired to be included.
34 integrated silicon solution, inc. www.issi.com rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a extended?mode?register?2?(emr2) the emr(2) controls refresh related features. the default value of the emr(2) is not defned, therefore the emr(2) must be programmed during initialization for proper operation. the emr(2) is written by asserting low on cs, ras, cas, we, high on ba1 and low on ba0, while controlling the states of address pins a0 - a11/a12. the ddr2 sdram should be in all bank precharge state with cke already high prior to writing into the emr(2). the mode register set command cycle time (tmrd) must be satisfed to complete the write operation to the emr(2). mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. emr(2) address field mode register ba1 1 ba0 0 a12 *1 0 a11 *1 0 a10 *1 0 a9 *1 0 a7 high temperature self-refresh rate enable 0 disable 1 enable *2 a8 *1 0 a7 srf a6 *1 0 0 0 a5* 1 a4 * 1 a2 a1 a0 ba [1:0] partial array self refresh for 4 banks a3 * 1 0 0 0 0 full array 00,01,10,11 01,10,11 10,11 11 00,01 00 -- -- 0 0 1 1/2 array a2 pasr *3 0 1 0 1/4 array 0 1 1 reserved a1 1 0 0 3/4 array 1 0 1 1/2 array a0 1 1 0 1/4 array 1 1 1 reserved notes: 1. a3-a6, a8-a12 are reserved for future use and must be set to 0 when programming the emr(2). 2. if the high temperature self-refresh mods is supported then controller can set the emr (2) [a7] bit to enable the self-refresh rate if tc > 85 o c while in self-refresh operation. t oper may not be violated. 3. if pasr (partial array self refresh) is enabled, data located in areas of the array beyond the specifed address range will be lost if self refresh is entered. data integrity will be maintained if tref conditions are met and no self refresh command is issued. extended?mode?register?3?(emr3) there is not an emr(3) defned. it is not necessary to issue an emrs command to this register (high on ba1 and ba0), and no effect results.
integrated silicon solution, inc. www.issi.com 35 rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a t ruth ?tables operation or timing that is not specifed is illegal, and after such an event, in order to guarantee proper operation, the dram must be powered down and then restarted through the speechifed initialization sequence before normal operation can continue. command? truth ? table function cke cs ras cas we ba1 ?-? ba0 a12, ? a11, ?a9 a10 a8-a0 notes previous cycle current cycle (extended) mode register set (load mode) h h l l l l ba op code 1, 2, 10 refresh (ref) h h l l l h x x x x 1 self refresh entry h l l l l h x x x x 1, 8 self refresh exit l h h x x x x x x x 1, 7, 8 l h h h single bank precharge h h l l h l ba x l x 1, 2 precharge all banks h h l l h l x x h x 1 bank activate h h l l h h ba row address 1, 2, 10 write h h l h l l ba x l column 1, 2, 3, 11 write with auto precharge h h l h l l ba x h column 1, 2, 3, 11 read h h l h l h ba x l column 1, 2, 3, 11 read with auto- precharge h h l h l h ba x h column 1, 2, 3, 11 no operation h x l h h h x x x x 1 device deselect h x h x x x x x x x 1 power down entry h l h x x x x x x x 1, 4 l h h h power down exit l h h x x x x x x x 1, 4 l h h h notes: 1. all ddr2 sdram commands are defned by states of cs, ras, cas , we and cke at the rising edge of the clock. 2. bank addresses ba0, ba1 (ba) determine which bank is to be operated upon. for (e)mrs ba selects an (extended) mode register. 3. burst reads or writes at bl=4 cannot be terminated or interrupted. see sections "reads interrupted by a read" and "writes interrupted by a write" for details. 4. the power down mode does not perform any refresh operations. the duration of power down is therefore limited by the refresh requirements 5. the state of odt does not affect the states described in this table. the odt function is not available during self refresh. see section 3.4.4. 6. x means h or l (but a defned logic level) 7. self refresh exit is asynchronous. 8. vref must be maintained during self refresh operation. 9. bax and axx refers to the msbs of bank addresses and addresses, respectively. 10. for standard page-size option, a12 is not used for row addressing, but is used for mrs and emr. (op code) 11. for reduced page-size option, a8 is not used for column addressing.
36 integrated silicon solution, inc. www.issi.com rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a clock ? enable?(cke)? truth ? table current? state 2 cke command?(n) 3 ras, ?cas, ?we, ? cs action?(n) 3 notes previous ? cycle 1 ? (n-1) current? cycle 1 ? (n) power down l l x maintain power-down 11, 13, 15 l h deselect or nop power down exit 4, 8, 11, 13 self refresh l l x maintain self refresh 11, 15,16 l h deselect or nop self refresh exit 4, 5, 9, 16 bank(s) active h l deselect or nop active power down entry 4, 8, 10, 11, 13 all banks idle h l deselect or nop precharge power down entry 4, 8, 10, 11,13 h l refresh self refresh entry 6, 9, 11,13 h h refer to the command truth table 7 notes: 1. cke (n) is the logic state of cke at clock edge n; cke (nC1) was the state of cke at the previous clock edge. 2. current state is the state of the ddr2 sdram immediately prior to clock edge n. 3. command (n) is the command registered at clock edge n, and action (n) is a result of command (n). 4. all states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 5. on self refresh exit deselect or nop commands must be issued on every clock edge occurring during the txsnr period. read commands may be issued only after txsrd (200 clocks) is satisfed. 6. self refresh mode can only be entered from the all banks idle state. 7. must be a legal command as defned in the command truth table. 8. valid commands for power down entry and exit are nop and deselect only. 9. valid commands for self refresh exit are nop and deselect only. 10. power down and self refresh cannot be entered while read or write operations, (extended) mode register set operations or precharge operations are in progress. 11. tckemin of 3 clocks means cke must be registered on three consecutive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. thus, after any cke transition, cke may not transition from its valid level during the time period of tis + 2 x tck + tih. 12. the state of odt does not affect the states described in this table. the odt function is not available during self refresh. 13. the power down does not perform any refresh operations. the duration of power down mode is therefore limited by the refresh requirements outlined in this datasheet. 14. cke must be maintained high while the ddrii sdram is in ocd calibration mode . 15. x means dont care (including foating around vref) in self refresh and power down. however odt must be driven high or low in power down if the odt function is enabled (bit a2 or a6 set to 1 in emr(1) ). 16. vref must be maintained during self refresh operation. data?mask? truth ? table name?(functional) dm dqs note write enable l valid 1 write inhibit h x 1 note: 1. used to mask write data, provided coincident with the corresponding data
integrated silicon solution, inc. www.issi.com 37 rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a deselect the deselect function (cs high) prevents new commands from being executed by the ddr2 sdram. the ddr2 sdram is effectively deselected. operations already in progress are not affected. deselect is also referred to as command inhibit. no? operation?(nop) the no operation (nop) command is used to instruct the selected ddr2 sdram to perform a nop (cs is low; ras, cas, and we are high). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. mode?register?set?(mrs?or?emrs) the mode registers are loaded via bank address and address inputs. the bank address balls determine which mode register will be programmed. see sections on mode register and extended mode registers. the mrs and emrs commands can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tmrd is met. activate the activate command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the bank address inputs determines the bank, and the address inputs select the row. this row remains active (or open) for accesses until a precharge command is issued to that bank. a precharge command must be issued before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active row. the value on the bank address inputs determine the bank, and the address provided on address inputs a0Cai (where ai is the most signifcant column address bit for a given confguration) selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. ddr2 sdram also supports the al feature, which allows a read or write command to be issued prior to trcd (min) by delaying the actual registration of the read/write command to the internal device by al clock cycles. write the write command is used to initiate a burst write access to an active row. the value on the bank select inputs selects the bank, and the address provided on inputs a0Cai (where ai is the most signifcant column address bit for a given confguration) selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. ddr2 sdram also supports the al feature, which allows a read or write command to be issued prior to trcd (min) by delaying the actual registration of the read/write command to the internal device by al clock cycles. input data appearing on the dq is written to the memory array subject to the dm input logic level appearing coincident with the data. if a given dm signal is registered low, the corresponding data will be written to memory; if the dm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location.
38 integrated silicon solution, inc. www.issi.com rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row activation a specifed time (trp) after the precharge command is issued, except in the case of concurrent auto precharge, where a read or write command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. after a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a precharge command is allowed if there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. however, the precharge period will be determined by the last precharge command issued to the bank. refresh refresh is used during normal operation of the ddr2 sdram and is analogous to cas -before-ras (cbr) refresh. all banks must be in the idle mode prior to issuing a refresh command. this command is nonpersistent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh controller. this makes the address bits a dont care during a refresh command. self?refresh the self refresh command can be used to retain data in the ddr2 sdram, even if the rest of the system is powered down. when in the self refresh mode, the ddr2 sdram retains data without external clocking. all power supply inputs (including vref) must be maintained at valid levels upon entry/exit and during self refresh operation. the self refresh command is initiated like a refresh command except cke is low. the dll is automatically disabled upon entering self refresh and is automatically enabled upon exiting self refresh. odt?(on-die? termination) the on-die termination feature allows the ddr2 sdram to easily implement a termination resistance (rtt) for each dq, dqs, and dqs signal. the odt feature can be confgured with the extended mode register set (emrs) command, and turned on or off using the odt input signal. before and after the emrs is issued, the odt input must be received with respect to the timings of taofd, tmod(max), taond; and the cke input must be held high throughout the duration of tmod(max). the ddr2 sdram supports the odt on and off functionality in active, standby, and power down modes, but not in self refresh mode. odt timing diagrams follow for active/standby mode and power down mode. emrs?to?odt?update? delay e m rs ck ck cm d no p no p no p no p no p od t tm od ,m ax tm od ,m in ol d se tti ng odt read y u pdate d rt t ta of d ti s ta on d
integrated silicon solution, inc. www.issi.com 39 rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a t0 t1 t2 t3 t4 t5 t aond ck ck ck e od t r t t t6 t aofd t is t is t aon,mi n t aon,ma x t ao f, mi n t ao f, ma x v alid v ih (ac) v il (ac) t is t0 t1 t2 t3 t4 t5 ck ck ck e od t r t t t6 t is t is t aonpd,mi n t aofpd,ma x t aonpd,ma x t aofpd,mi n valid v ih (ac) v il (ac) odt on/off ti ming for active/standby mode odt on/off ti ming for power-down mode
40 integrated silicon solution, inc. www.issi.com rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a clock ?(mhz) speed?grade cl-trcd-trp order ? part?no. package 266 ddr2-533c 4-4-4 is43dr32801a-37cbl 126 ball bga, lead-free 200 ddr2-400b 3-3-3 is43dr32801a-5bbl 126 ball bga, lead-free ordering?i nformation?-? v dd ?1.8v ? reduced? page? size: ?is43dr32801a commercial ? range: ? tc?=?0 o c?to?+85 o c, ? t a ?=?0 o c?to?+70 o c? clock ?(mhz) speed?grade cl-trcd-trp order ? part?no. package 266 ddr2-533c 4-4-4 is43dr32801a-37cbli 126 ball bga, lead-free 200 ddr2-400b 3-3-3 is43dr32801a-5bbli 126 ball bga, lead-free industrial? range: ? tc?=?-40 o c?to?+95 o c, ? t a ?=?-40 o c?to?+85 o c? please contact issi for availability of a2 option. clock ?(mhz) speed?grade cl-trcd-trp order ? part?no. package 266 ddr2-533c 4-4-4 IS43DR32800A-37CBL 126 ball bga, lead-free 200 ddr2-400b 3-3-3 is43dr32800a-5bbl 126 ball bga, lead-free ordering?i nformation?-? v dd ?1.8v ? standard ? page? size: ?is43dr32800a commercial ? range: ? tc?=?0 o c?to?+85 o c, ? t a ?=?0 o c?to?+70 o c? clock ?(mhz) speed?grade cl-trcd-trp order ? part?no. package 266 ddr2-533c 4-4-4 IS43DR32800A-37CBLi 126 ball bga, lead-free 200 ddr2-400b 3-3-3 is43dr32800a-5bbli 126 ball bga, lead-free industrial? range: ? tc?=?-40 o c?to?+95 o c, ? t a ?=?-40 o c?to?+85 o c? clock ?(mhz) speed?grade cl-trcd-trp order ? part?no. package 200 ddr2-400b 3-3-3 is46dr32801a-5bbla1 126 ball bga, lead-free automotive ? range, ?a1: ? tc?=?-40 o c?to?+95 o c, ? t a ?=?-40 o c?to?+85 o c? clock ?(mhz) speed?grade cl-trcd-trp order ? part?no. package 200 ddr2-400b 3-3-3 is46dr32801a-5bbla2 126 ball bga, lead-free automotive ? range, ?a2: ? tc?=?-40 o c?to?+105 o c, ? t a ?=?-40 o c?to?+105 o c?
integrated silicon solution, inc. www.issi.com 41 rev.? 00e 09/08/2010 is43dr32800a, is43/46dr32801a 11/09/2007 package outline 7 . package dimensions

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